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Abstract

The Median filter is an effective method for the removal of impulse-based noise from the images. This paper suggests an optimized architecture for filter implementation on Spartan3 FPGA Image Processing Kit. A 3x3 sliding window algorithm is used as the base for filter operation. Partial implementation is done via soft core processor.

Demonstration Video

 

Block Diagram for FPGA based Median Filter Implementation using Spartan3 FPGA Image Processing Kit



Bgim_Median_Filter_imp

Tool required

Software:

⇛Xilinx ISE 10.1i or above

⇛Xilinx EDK 10.1i or above

⇛VB GUI to display output

Language:

⇛VHDL, System C

Hardware:

Spartan3 FPGA Image Processing Kit

⇛JTAG Cable

⇛PC

⇛Serial Cable

Introduction:

An image is stored in the form of 2D matrix of pixel values. We have referred sliding window algorithm. The median is defined as the middle of a group of numbers when the numbers are sorted. The group should contain odd number of elements. For the 2D image, a standard median operation is implemented by sliding a window of odd size (e.g. 3x3 windows) over an image.

A 3x3 window size is chosen which is considered effective for most commonly used image sizes. At each position of the window, the nine pixels values inside that window are copied and sorted. The value of the central pixel of the window is replaced with the median value of the nine pixels in the window. When applied on Grayscale images, pixels are ranked for their brightness. When applied on Color scale images, the pixel whose red, green, and blue components have the smallest sum of squared differences from the color coordinates of its neighbors is then chosen to replace the central pixel of the neighborhood.

Soft Processor Core

A soft processor core is a microprocessor core that can be wholly implemented using logic synthesis. It can be implemented via FPGA. Custom peripheral blocks are interfaced with a soft Microblaze Processor

Local Bus (PLB) is used for this interfacing. In the proposed implementation, the input image stored in DDR2 memory is converted to HEX data format by the soft processor. The filtered image is converted back to its ASCII form again by the soft processor

Output Image for Median Filtering using Spartan3 FPGA Image Processing Kit

Out_Median_Filter_Imp


Output Image for Median Filtering using Spartan3 FPGA Image Processing Kit

Output Image for Median Filtering using Spartan3 FPGA Image Processing Kit


Output Image for Median Filtering using Spartan3 FPGA Image Processing Kit

                       Output Image for Median Filtering using Spartan3 FPGA Image Processing Kit

 Output Image for Median Filtering using Spartan3 FPGA Image Processing Kit

Source Code

C Code Noise Removal Median Filter Using Spartan3 FPGA Image Processing Kit

#include 
#include 
#include <rose_noise.h>
#define R 128

#define C 128
#define ROW 128
#define COL 128
#define ROW1 128
#define COL1 128
#define Len 16384

int Dataset[9];
int REDB[R][C];

int INPUT[R][C];
int arr1[3];
int n=9,t;
int Z_max,Z_min,Z_med;
int bitcount=0;
int SR0,SR1,SR2,SR3,SR4,SR5,SR6,SR7,SR8,SR9;
int Z_xy ;
int REDN[ROW][COL];
int Sliding_windowr[3][3];
int RED[ROW][COL];
int RED1[ROW1][COL1];
int SR[9];
float bbr;
float median1();

float median1(int SR1,int SR2,int SR3,int SR4,int SR5,int SR6,int SR7,int SR8)

{
int i,j;
float median;
int arr[8];

arr[0]=SR1;
arr[1]=SR2;
arr[2]=SR3;
arr[3]=SR4;
arr[4]=SR5;
arr[5]=SR6;
arr[6]=SR7;
arr[7]=SR8;

for (i=0;i<=n-1;i++)
{

for(j=0;j<=n-1;j++)
{
if (arr[j]<=arr[j+1])
{
t=arr[j];
arr[j]=arr[j+1];

arr[j+1]=t;
}
else
continue;
}
}
if (n%2==0)
{
median=(arr[n/2]+arr[n/2+1])/2.0;
}
else
{
median=arr[n/2+1];
}

return (median);

}
///////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////
void main()
{
int i,j,m;
char ch;

int AA;
int valc;
int len=127;
/////////////////////////////////input

for( i=0;i<R;i++)
{
for( j=0;j<C;j++)
{
INPUT[i][j]=hai[i][j];
xil_printf("%d\n",INPUT[i][j]);
}

}
//////////////////////////////////////

for(i=0;i<ROW;i++)
{
for (j=0;j<COL;j++)
{
if (i==0 & j==0)
{
}          					
else if (i==0 & j==len)
{

}
else if (i==len & j==0)
{
			
}
else if (j==len & i==len)
{
		
}
else if (i==1)
{	

}
else if (i==len)
{

}
else if (j==len)
{

}
else if (j==1)
{

}

else
{ 							

Sliding_windowr[1][1]=INPUT[i-1][j-1];
Sliding_windowr[1][2]=INPUT[i-1][i];
Sliding_windowr[1][3]=INPUT[i-1][i+1];
Sliding_windowr[2][1]=INPUT[i][j-1];
Sliding_windowr[2][2]=INPUT[i][j];
Sliding_windowr[2][3]=INPUT[i][j+1];
Sliding_windowr[3][1]=INPUT[i+1][j-1];
Sliding_windowr[3][2]=INPUT[i+1][j];
Sliding_windowr[3][3]=INPUT[i+1][j+1];

//           		disp(Sliding_window);

SR1=Sliding_windowr[1][1];
SR2=Sliding_windowr[1][2];
SR3=Sliding_windowr[1][3];
SR4=Sliding_windowr[2][1];
//SR5=Sliding_windowr[2][2];
SR5=Sliding_windowr[2][3];
SR6=Sliding_windowr[3][1];
SR7=Sliding_windowr[3][2];
SR8=Sliding_windowr[3][3];
bbr=median1(SR1,SR2,SR3,SR4,SR5,SR6,SR7,SR8);

}	
RED1[i][j]=bbr;
}
}

for ( i=0;i<ROW1;i++)
{
for( j=0;j<COL1;j++)
{
xil_printf("%d\n",RED1[i][j]);					
}						
}
}
//end of main

Conclusion

An Image filtering is a necessary step in image processing. Median filter intended to reduce impulse noise from the image is implemented on Spartan3 FPGA Image Processing Kit. The proposed optimized architecture for the filter saves the hardware resources on FPGA