FPGA Implementation of AES Algorithm using Spartan6 FPGA Project Kit

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AES Algorithm using Spartan6 FPGA Project Kit
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FPGA Implementation of AES Algorithm using Spartan6 FPGA Project Kit
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Abstract

With the current ubiquity of computer networks, distributed systems in general, and the Internet in particular, cryptography has become an enabling technology to secure the information infrastructures we are building, using, and counting on in daily life. In present days, almost every relevant communication system requires secure data transfer in order to maintain the privacy of the transmitted message. Hardware implementation on FPGA offers a quicker and customizable solution. I use Very High Speed Integrated Circuit Hardware Decryption Language (VHDL) for synthesizing logic design. The existing project uses Spartan6 FPGA Project Kit which is an integrated circuit development platform based on the Xilinx Spartan 6 FPGA.

 

Tool required

Software:

  • Xilinx ISE 14.7i

Language:

  • Verilog

Hardware:

  • Spartan6 FPGA kit
  • Serial Cable
  • PC
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