FPGA based Median Filter Implementation using Spartan3 FPGA Image Processing Kit
The Median filter is an effective method for the removal of impulse-based noise from the images. This paper suggests an optimized architecture for filter implementation on Spartan3 FPGA Image Processing Kit.
Shipping : 3 to 4 working days from the Date of purchase
Complete Hardware Kit
Demo Video-Embedded Below
!!! Online Support !!!
100 in stock
The Median filter is an effective method for the removal of impulse-based noise from the images. This paper suggests an optimized architecture for filter implementation on Spartan3 FPGA Image Processing Kit. A 3×3 sliding window algorithm is used as the base for filter operation. Partial implementation is done via soft core processor.
Block Diagram for FPGA based Median Filter Implementation using Spartan3 FPGA Image Processing Kit
- Xilinx ISE 10.1i or above
- Xilinx EDK 10.1i or above
- VB GUI to display output
- VHDL, System C
- Spartan3 FPGA Image Processing Kit
- JTAG Cable
- Serial Cable
An image is stored in the form of 2D matrix of pixel values. We have referred sliding window algorithm. The median is defined as the middle of a group of numbers when the numbers are sorted. The group should contain odd number of elements. For the 2D image, a standard median operation is implemented by sliding a window of odd size (e.g. 3×3 windows) over an image.
A 3×3 window size is chosen which is considered effective for most commonly used image sizes. At each position of the window, the nine pixels values inside that window are copied and sorted. The value of the central pixel of the window is replaced with the median value of the nine pixels in the window. When applied on Grayscale images, pixels are ranked for their brightness. When applied on Color scale images, the pixel whose red, green, and blue components have the smallest sum of squared differences from the color coordinates of its neighbors is then chosen to replace the central pixel of the neighborhood.
Soft Processor Core
A soft processor core is a microprocessor core that can be wholly implemented using logic synthesis. It can be implemented via FPGA. Custom peripheral blocks are interfaced with a soft Microblaze Processor
Local Bus (PLB) is used for this interfacing. In the proposed implementation, the input image stored in DDR2 memory is converted to HEX data format by the soft processor. The filtered image is converted back to its ASCII form again by the soft processor
Output Image for Median Filtering using Spartan3 FPGA Image Processing Kit
An Image filtering is a necessary step in image processing. Median filter intended to reduce impulse noise from the image is implemented on Spartan3 FPGA Image Processing Kit. The proposed optimized architecture for the filter saves the hardware resources on FPGA