Power has become a primary consideration during hardware design. Dynamic power can contribute up to 50% of the total power dissipation. Clock-gating is the most common RTL optimization for reducing dynamic power. By applying Effective clock-gating technique on RISC processor adds additional logic to the existing synchronous circuit to prune the clock tree, thus disabling the portions of the circuitry that are not in use. Here in this project designed and developed efficient RISC CPU Interrupt controller unit ,Port controller and Program Flow Controller of an RISC Processor and clock gating technique applied to designed units. Combinational and Sequential clock-gating selectively suspend clocking while the block continues to produce output. In typical designs, combinational clock-gating can reduce dynamic power by about 15-to-20%.On the other hand sequential clock-gating can save significant power, typically reducing switching activity by 10-to-25% on a given block. Thus, different RTL techniques are used to reduce the power dissipation of a processor. The whole project captured in VHDL and implemented on targeted FPGA chip and observed the power using Xilinx Xpower tools.
Clock gating is a popular technique used in many synchronous circuits for reducing dynamic power dissipation.
Clock gating saves power
Xilinx ISE 14.7