Design of Efficient Han-Carlson-Adder

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Design of Efficient Han-Carlson-Adder
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Design of Efficient Han-Carlson-Adder
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Binary addition is one of the most important arithmetic function in modern digital VLSI systems. Adders are extensively used as DSP lattice filters. The ripple carry adders are replaced by the parallel prefix adder to decrease the delay. The requirement of the adder is fast and secondly efficient in terms of power consumption and chip area.

Proposed System

Han-Carlson prefix tree is same as that of Kogge -Stone's structure. The different is it uses much less cells and wire tracks compare to that of Kogge-Stone. Han-Carlson prefix tree is nothing but the sparse version of Kogge-Stone prefix tree. The Han-Carlson adder consists of a good trade-off between fan-out, number of black cells and number of logic levels. Due to this, HanCarlson adder can achieve similar speed performance as that of Kogge-Stone adder, at lower power consumption with area.


PRE PROCESSING : In the pre processing stage generate (Gi) and propagate (Pi) signals are calculated.

Gi = a and b & Pi = a xor b

PREFIX PROCESSING : Calculations of all carry signals:

G(i:j) = G(i:k) +P(i:k) . G(k-1):j P(i:j) = P(i:k) . P(k-1:j)

Tools Required:



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