DESIGN AND ANALYSIS OF MAJORITY LOGIC BASED APPROXIMATE ADDERS AND MULTIPLIERS

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LOGIC BASED APPROXIMATE ADDERS AND MULTIPLIERS
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DESIGN AND ANALYSIS OF MAJORITY LOGIC BASED APPROXIMATE ADDERS AND MULTIPLIERS
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INTRODUCTION:

Now a days, the main obstacles to attain high performance, power dissipation is increasingly been investigated for IC design. Approximate computing is a promising technique to reduce power consumption and improve performance of circuit. Approximate computer arithmetic circuits based on CMOS technology have been extensively studied. Designs of approximate adders, multipliers and dividers for both fixed point and floating-point formats have been proposed. All of these technologies rely on majority logic (ML) as digital design framework; this is different from conventional Boolean logic. The majority gate performs a multi input logic operation. It is expected that significant improvement in power consumption could be achieved by applying approximate computing also to emerging nanotechnologies.

EXISTING SYSTEM:

Exact FA (EFAs):

Exact Full Adders are designed by Majority Logic gates

Drawbacks:

  • More majority gates (MV),
  • More inverters (INV),
  • Delay (D).

PROPOSED SYSTEM:

Multi bit MLAFAs:

2-bits, 4- bit MLAFAs are proposed by utilizing two methods:

Method 1: The proposed and the previous 1-bit MLAFAs

Method 2: It is based on a truth table reduction process for the 2-bit design.

Multi-bit MLAFAs are also designed by cascading the proposed designs.

Multi bit MLAMs: The MLAM, a 2 × 2 design with complement bits is proposed. Furthermore, complement bit selection is analyzed as function of the size of a multiplier; a so-called influence factor is introduced to assess the importance of different complement bits.

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