Multipliers play an important role in today’s digital signal processing and various other applications. The common multiplication method is “add and shift” algorithm. In parallel multipliers number of partial products to be added is the main parameter that determines the performance of the multiplier.
Modified Booth encoder:
The Booth algorithm has been used to improve the sign correction issues of signed number multiplication however, the original Booth algorithm does not reduce the number of PPs. It reduces the number of PP rows by half. The complexity of the parallel multiplier is reduced signiﬁcantly by applying modified booth encoder. Let A = aN−1aN−2 ··· a2a1a0 be the multiplicand and B = bN−1bN−2 ···b2b1b0 be the multiplier. The multiplier bits are encoded; so they are grouped in sets of three adjacent bits.
Proposed approximate booth encoder
Two approximate Booth encoders are designed based on the conventional modiﬁed Booth encoding method and the new modiﬁed Booth encoding method, respectively. Radix-4 Approximate MBE The K-map of the radix-4 approximate modiﬁed Booth encoder i.e., appij6−1, with 6 errors in the Kmap where 0 denotes an entry in which a ‘1’ is replaced by a ’0’ and ‘1’ denotes a ’0’ entry that has been replaced by a ‘1’ This approximate design relies on the property that the truth table is asymmetrical as possible for a design with the least complexity.
This project has studied the design of approximate redundant binary multipliers and the following conclusion can be drawn: The proposed approximate Booth encoders on conventional exact Booth encoders(R4AMBE6) and new exact Booth encoders (R4ANMBE6) have moderate error and energy consumption; Also they achieve a very good tradeoff between error and performance. The two proposed RB 4:2 compressors (ARBC-1 and ARBC-2) reduce the energy consumption by over 47% and 64%, respectively, compared with ERBC.