After installing Xilinx ISE 8.1 i software, go to Start menu
Start >>Programs >> Xilinx ISE 8.1 i >>Project Navigator (or) double click on " Xilinx ISE 8" desktop icon (refer Figure-1). A Window shown in Figure-2 will appear.
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Create a new ISE project which will target the FPGA device on the Spartan-3 TYRO/PRIMER board. To create a new project:
1. Select File >> New Project... The New Project Wizard appears.(refer figure 3)
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2. New Project wizard window shown in Figure -4 will appear. In the Name field, enter your project name and enter the location where you want to create the project in the Location field (NOTE: don’t use c drive or desktop). In the Top-Level Module select HDL and click Next (refer Figure-5).
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3. A window given in Figure-6 will appear. Fill in the properties in the table as shown below:
Then click "Next" (refer Figure- 6, 7, 8) and then "Finish" (refer Figure- 9).
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4. A window given in Figure-10 will appear. Select Project menu >> New Source (refer Figure-11). A window given in Figure-12 will appear. Then select VHDL module, and specify the file name in appropriate field as shown in figure-13 and Click Next. If you want you can give inputs & outputs in the appropriate positions in the window shown in Figure -14.You can also skip these information by simply clicking Next button and click Finish (refer Figure - 15).
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5. A window shown in Figure-16 will appear. You can type your VHDL code in the right side of window and Save it by clicking on the save button (refer Figure-17). Now in the “Processes:”window double click Synthesize-XST as shown in Figure-18.
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Note: You must correct any errors found in your source files. You can check for errors in the Console tab of the Transcript window. If you continue without valid syntax, you will not be able to simulate or synthesize your design.
6 .Assigning Pin Location Constraints Specify the pin locations for the ports of the design so that they are connected correctly on the Spartan-3 TYRO/PREMIER board.
To constrain the design ports to package pins, do the following before that refer the LED & SWITCH PIN DETAILS in before pages or see board for giving the pin location.
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8. There are two ways of downloading the program into the target hardware, one is generating the.bit file for downloading into the FPGA device and the other is generating the.mcs file for downloading into the PROM device.
9. To download the program as .bit file in Boundary Scan mode, do the following steps:
i) Shunt of Jumper J2 of must be in S3 position for FPGA selection.
ii) In the Project Navigator window and click Implement design in Processes:category(refer Figure-22).
Notice that after Implementation is complete, the Implementation processes have a green check mark next to them indicating that they completed successfully without Errors or Warnings.
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10. After implement design has become successful (refer Figure-23), click Generate Programming File (refer Figure- 24). After generate programming file has been completed successfully click Manage Configuration Project (IMPACT) (refer Figure-25).
11. Download Design to the Spartan™-3 TYRO/PRIMER Kits.
This is the last step in the design verification process.
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If you get a Warning message, click OK.
When programming is complete, the Program Succeeded message is displayed.
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