How to Interface PS/2 with Spartan-3 TYRO FPGA

Interfacing PS2 with Spartan-3 TYRO FPGA

Tags: Interfacing PS/2 with Spartan3 TYRO FPGA, Pin Assignment of PS/2 with Spartan3 TYRO FPGA, Schematics to Interface PS/2 with Spartan3 FPGA, VHDL Code for PS/2 using Spartan3 TYRO FPGA, VHDL code for ps/2 keyboard interface, Schematics to interface ps/2 with Spartan3 fpga
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PC mouse and the keyboard use the two-wire PS/2 serial bus to communicate with a host device.

Interfacing PS/2 with Spartan-3 TYRO FPGA

The Spartan3 Tyro FPGA Kit includes PS/2 port for mouse/keyboard interface and it is the standard 6-pin mini-DIN connector, labeled U12 on the board. Figure 6 shows the PS/2 connector, and Table shows the signals on the connector. Only pins 1 and 5 of the connector attach to the FPGA I/O lines.

Pin Assignment with Spartan-3 TYRO FPGA








Schematics to Interface PS/2 with Spartan-3 FPGA

ps2 tyro

VHDL Code for PS/2 using Spartan-3 TYRO FPGA



library IEEE;





---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;


entity key is

port( data: in std_logic;

                        pclk: in std_logic;

                        l1 : out std_logic;

                        l2 : out std_logic;

                        l3 : out std_logic;

                        l4 : out std_logic;

                        l5 : out std_logic;

                        l6 : out std_logic;

                        l7 : out std_logic;

                        l8 : out std_logic);

end key;


                        architecture Behavioral of key is

type state is (state1,state2,state3,state4,state5,state6,state7,state8,state9,state10,state11);

signal ps,ns : state;

signal store : std_logic_vector(7 downto 0):="00000000";

signal start,parity,stop : std_logic;




if pclk'event and pclk = '1' then


ps <= ns;

end if;

if pclk'event and pclk = '0' then

if ps = state1 then

stop <= data;

ns <= state2;

elsif ps = state2 then

store(0) <= data;

ns <= state3;

elsif ps = state3 then

store(1) <= data;

ns <= state4;

elsif ps = state4 then

store(2) <= data;

ns <= state5;

elsif ps = state5 then

store(3) <= data;

ns <= state6;

elsif ps = state6 then

store(4) <= data;

ns <= state7;

elsif ps = state7 then

store(5) <= data;

ns <= state8;

elsif ps = state8 then

store(6) <= data;

ns <= state9;

elsif ps = state9 then

store(7) <= data;

ns <= state10;

elsif ps = state10 then

parity <= data;

ns <= state11;

elsif ps = state11 then

stop <= data;

ns <= state1;


end if;

end if;

end process;



l1 <= store(0);

l2 <= store(1);

l3 <= store(2);

l4 <= store(3);

l5 <= store(4);

l6 <= store(5);

l7 <= store(6);

l8 <= store(7);

end process;

end Behavioral;



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