After installing Xilinx ISE 11.4 i software, go to Start menu
Start >> Programs >> Xilinx ISE Design Suite 11.1 i >> Project Navigator (or) double click on ISE icon desktop icon. A Window shown in below will appear.
Create a new ISE project which will target the FPGA device on the Spartan-3 PRIMER board.
To create a new project:
1. Select File >> New Project... The New Project Wizard appears.(refer figure 2) In the Name field, enter your project name and enter the location where you want to create the project in the Location field (NOTE: don’t use c drive or desktop). In the Top-Level Source Type select HDL and click Next.
3. Create New Source window given in Figure- will appear. Select VHDL module, and specify the file name in appropriate field as shown in figure- and Click Next.
4. In the Define Module specify I/O port name and direction.
5. Click Next button to display Summary and click Finish.
6. Newly created Source will appear as lcd.vhd, click Next,
7. Skip “Add Existing Sources” and click Next.
8. Finally Project Summary window will appear. Click Finish.
9. The Project Navigator window consist of four panes:
10. Type the following lcd.vhd code in editor pane and save it.
11. Change the source from Implementation to Behavioral Simulation and check syntax by double click Behavioral check syntax option in process pane. Process "Check Syntax" completed successfully appears in transcript pane.
12. Create VHDL Test Bench by selecting New Source Wizard and name it as tb_lcd.vhd.
13. Now automatically created VHDL test bench appear as shown in figure. Modify clock_Period from 10ns to 20ns and save it.
14. Right Click Simulate Behavioral Model and Click Run to open ISim.
15. ISim appear as shown in figure.
16. Type run 500ms in console pane after that simulation will produce PANTECH SOLUTION in lcd_data line.
17. After simulation, change the source from simulation to implementation and then Right click and run synthesis. The ISE® software includes Xilinx Synthesis Technology (XST), which synthesizes VHDL, Verilog, or mixed language designs to create Xilinx®-specific netlist files known as NGC files.
18. Editor pane display Device Utilization Summary
19. Run I/O Pin Planning under User Constraints for FPGA Pin definition.
20. Planahead window open for Pin definition. Select I/O Port and define its pin at I/O Port Bus Properties and click Apply.
21. After assigning all I/O Pins save and close it.
22. The following UCF file appears in the Editor Plan .
NET "clock" LOC = P55;
NET "lcd_data" LOC = P108;
NET "lcd_data" LOC = P112;
NET "lcd_data" LOC = P113;
NET "lcd_data" LOC = P116;
NET "lcd_data" LOC = P118;
NET "lcd_data" LOC = P119;
NET "lcd_data" LOC = P122;
NET "lcd_data" LOC = P123;
NET "lcd_en" LOC = P107;
NET "lcd_rs" LOC = P104;
NET "lcd_rw" LOC = P105;
By selecting lcd.ucf in Source and edit constraints in Process pane. Pin Definition can be displayed.
23. Next step is Implementation, which comprises the following steps:
24. To open IMPACT window for downloading program file in to FPGA, Click Manage Configuration Project under Configure Target Device.
25. Double Click Boundary Scan on left pane and then Right Click right pane and select Initialize chain.
26. Now FPGA Board Devices will appear ( XC3S200, XCF04S) FPGA and PROM. It ask for bit file. Select lcd.bit file
27. After Bit file selection, Right Click XC3S200 and select Program.
28. After Successful Completion. It will Display Program Succeeded.
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