Getting started with XILINX ISE 11.4i

Tags: Working with Xilinx ISE 11 software,
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Getting Started with Xilinx ISE 11.4 i

After installing Xilinx ISE 11.4 i software, go to Start menu

Start >> Programs >> Xilinx ISE Design Suite 11.1 i >> Project Navigator (or) double click on ISE icon desktop icon. A Window shown in below will appear.


Create a New Project

Create a new ISE project which will target the FPGA device on the Spartan-3 PRIMER board.

To create a new project:

1. Select File >> New Project... The New Project Wizard appears.(refer figure 2) In the Name field, enter your project name and enter the location where you want to create the project in the Location field (NOTE: don’t use c drive or desktop). In the Top-Level Source Type select HDL and click Next.



  • Product Category: All
  • Family: Spartan3
  • Device: XC3S200
  • Package: TQ144 selected.
  • Speed Grade: -4
  • Top-Level Module Type: HDL
  • Synthesis Tool: XST (VHDL/Verilog)
  • Simulator: ISE Simulator (VHDL/Verilog)
  • Preferred language: VHDL


3. Create New Source window given in Figure- will appear. Select VHDL module, and specify the file name in appropriate field as shown in figure- and Click Next.


4. In the Define Module specify I/O port name and direction.


5. Click Next button to display Summary and click Finish.


6. Newly created Source will appear as lcd.vhd, click Next,


7. Skip “Add Existing Sources” and click Next.


8. Finally Project Summary window will appear. Click Finish.


9. The Project Navigator window consist of four panes:

  • A source pane that shows the organization of the source files that make up your design. There are four tabs so you can view the functional modules, source files, different
    snapshots (or versions) of your project, or the HDL libraries for your project.
  • A process pane that lists the various operations you can perform on a given object in the source pane.
  • A transcript pane that displays the various messages from the currently running process.
  • An editor pane where you can enter HDL code, schematics, state diagrams, etc.


10. Type the following lcd.vhd code in editor pane and save it.





library IEEE;





entity lcd is

   Port ( clock : in STD_LOGIC;

           lcd_en : out STD_LOGIC;

           lcd_rs : out STD_LOGIC;

           lcd_rw : out STD_LOGIC;

           lcd_data : out STD_LOGIC_VECTOR (7 downto 0));

end lcd;


architecture Behavioral of lcd is

constant N: integer :=22;

type arr is array (1 to N) of std_logic_vector(7 downto 0);

constant datas : arr :=   (X"38",X"0c",X"06",X"01",X"C0",X"50",x"41",x"4e",x"54",x"45",x"43",

x"48",x"20",x"53",x"4f", x"4c",x"55", x"54",x"49",x"4f",x"4e",X"53"); --command and data to display                                            


lcd_rw <= '0'; ----lcd write


variable i : integer := 0;

variable j : integer := 1;


if clock'event and clock = '1' then

if i <= 1000000 then

i := i + 1;

lcd_en <= '1';

lcd_data <= datas(j)(7 downto 0);

elsif i > 1000000 and i < 2000000 then

i := i + 1;

lcd_en <= '0';

elsif i = 2000000 then

j := j + 1;

i := 0;

end if;

if j <= 5 then

lcd_rs <= '0';   ---command signal

elsif j > 5   then

lcd_rs <= '1';   ----data signal

end if;

if j = 22 then ---repeated display of data

j := 5;

end if;

end if;

end process;

end Behavioral;




11. Change the source from Implementation to Behavioral Simulation and check syntax by double click Behavioral check syntax option in process pane. Process "Check Syntax" completed successfully appears in transcript pane.


12. Create VHDL Test Bench by selecting New Source Wizard and name it as tb_lcd.vhd.


13. Now automatically created VHDL test bench appear as shown in figure. Modify clock_Period from 10ns to 20ns and save it.

modify-clock period

14. Right Click Simulate Behavioral Model and Click Run to open ISim.


15. ISim appear as shown in figure.



16. Type run 500ms in console pane after that simulation will produce PANTECH SOLUTION in lcd_data line.

lcd data-line

17. After simulation, change the source from simulation to implementation and then Right click and run synthesis. The ISE® software includes Xilinx Synthesis Technology (XST), which synthesizes VHDL, Verilog, or mixed language designs to create Xilinx®-specific netlist files known as NGC files.


18. Editor pane display Device Utilization Summary

  • Number of slices
  • Number of slice Flip Flops
  • Number of 4 input LUTs
  • Number of Bonded IOs
  • Number of GCLKs


19. Run I/O Pin Planning under User Constraints for FPGA Pin definition.


20. Planahead window open for Pin definition. Select I/O Port and define its pin at I/O Port Bus Properties and click Apply.


21. After assigning all I/O Pins save and close it.


22. The following UCF file appears in the Editor Plan .

NET "clock" LOC = P55;
NET "lcd_data[0]" LOC = P108;
NET "lcd_data[1]" LOC = P112;
NET "lcd_data[2]" LOC = P113;
NET "lcd_data[3]" LOC = P116;
NET "lcd_data[4]" LOC = P118;
NET "lcd_data[5]" LOC = P119;
NET "lcd_data[6]" LOC = P122;
NET "lcd_data[7]" LOC = P123;
NET "lcd_en" LOC = P107;
NET "lcd_rs" LOC = P104;
NET "lcd_rw" LOC = P105;

By selecting lcd.ucf in Source and edit constraints in Process pane. Pin Definition can be displayed.


23. Next step is Implementation, which comprises the following steps:

  • Translate - merges the incoming netlists and constraints into a Xilinx® design file.
  • Map - fits the design into the available resources on the target device, and optionally, places the design.
  • Place and Route - places and routes the design to the timing constraints.
  • Generate Programming File - creates a bitstream file that can be downloaded to the device.


24. To open IMPACT window for downloading program file in to FPGA, Click Manage Configuration Project under Configure Target Device.


25. Double Click Boundary Scan on left pane and then Right Click right pane and select Initialize chain.


26. Now FPGA Board Devices will appear ( XC3S200, XCF04S) FPGA and PROM. It ask for bit file. Select lcd.bit file


27. After Bit file selection, Right Click XC3S200 and select Program.


28. After Successful Completion. It will Display Program Succeeded.


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