How to Interface EEPROM with Spartan-3 Primer FPGA

Interfacing EEPROM with Spartan-3 Primer FPGA

Tags: VHDL code for EEPROM, Schematics to interface EEPROM with Spartan3 fpga,
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The AT24C01A/02/04/08/16 provides 1024/2048/ 4096/8192/16384 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential.

Interfacing EEPROM with Spartan-3 Primer FPGA

The Spartan-3 Primer board has I2C EEPROM, indicated as in Figure. The FPGA pins that drive the EEPROM port appear in Table. The SCL is clock input and is used to synchronize EEPROM with FPGA for various operations. When data is to be read or write, first a start condition is created followed by device address, byte address and the data itself. Finally a stop condition is provided. The start condition occurs when SDA and SCL get high to low simultaneously. The stop condition is when SDA remains low while SCL goes from high to low. The data is read or written between the start and stop conditions on every transition of SCL from high to low.

Pin Assignment with Spartan-3 Primer FPGA








Schematics to Interface EEPROM with Spartan-3 FPGA



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