How to Interface DC Motor with FPGA/CPLD UDB

Interfacing DC motor with FPGA-CPLD UDB

Tags: VHDL code for dc motor interface, Schematics to interface dc motor with Spartan3, Spartan3e fpga, Altera cyclone3 Fpga, xc95288xl cpld,
Overall rating
DC Motor

A DC motor is an electric motor that runs on direct current (DC) electricity. DC motors were used to run machinery, often eliminating the need for a local steam engine or internal combustion engine.

Interfacing DC Motor with FPGA/CPLD UDB

The Universal Development board has external DC motor interfacing, indicated as in Figure. 5V DC Motor speed has controlled through PWM signal. Motor can run both clockwise/counter clockwise, Motor speed controlled by varying ENA (duty cycle) signal through program. Reverse the direction of rotation by reversing the polarity of input.

Pin Assignment with FPGA/CPLD UDB


DC Motor(5V)

PIN NAME                    

Dc Motor PWM1


Dc Motor PWM2


Dc Motor Enable



Circuit Diagram to Interface DC Motor with FPGA/CPLD
VHDL Program for DC Motor using FPGA/CPLD


Title : Program for DC Motor






library IEEE;





---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;



entity dc is

port ( clk : in std_logic;

       rst : in std_logic;

                        enable : out std_logic;

                        output1 : out std_logic;

                        output2 : out std_logic);

end dc;


architecture Behavioral of dc is




variable i : integer := 0;


if rst = '1' then

if clk'event and clk = '1' then

enable <= '1';

if i <= 1005000 then

i := i + 1;


output1 <= '0';

output2 <= '0';

elsif i > 1005000 and i < 1550000 then

i := i + 1;

output1 <= '1';

output2 <= '0';

elsif i = 1550000 then

i := 0;

end if;

end if;

end if;

end process;

end Behavioral;



Join the World's Largest Technical Community

we respect your privacy.