Clock gating aware low power ALU design and implementation on FPGA.

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Clock gating aware low power ALU design
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Clock gating aware low power ALU design and implementation on FPGA.
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Abstract

This paper deals with the design and implementation of a Clock Gating Aware Low Power  Arithmetic and Logic Unit that has been developed as part of low power processor design in the platform Xilinx ISE 14.2 and  synthesized on 90nm Spartan-3 FPGA. Clock power contributes 45-60 percent of total dynamic power. Hence, clock power reduction is necessary in low power design. In this paper, we analyze theoretical 93.75% clock power reduction in ALU using clock gating techniques. On simulator, we achieved 88.23% clock power reduction using latch based clock gating and 70.58% clock power reduction using latch free clock gating.

Applications

Modern CPUs contain very powerful and complex ALUs. In addition to ALUs, modern CPUs contain a control unit (CU)

Advantages

The arithmetic logic unit is that part of the CPU that handles all the calculations the CPU may need. Most of these operations are logical in nature.

Software Used

Xilinx ISE 14.7

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