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Buzzer Interface with CPLD Development Kit

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Piezo buzzer is an electric component that comes in different shapes and sizes, which can be used to create sound waves when provided with electrical signal. piezo buzzer requires a square wave to produce a tone.

Interfacing Piezo buzzer with CPLD Development Kit

The CPLD Development Kit has Piezo buzzer, indicated as in Figure. Buzzer is driven by transistor Q1. FPGA can create sound by generating a PWM(Pulse Width Modulated) signal – a square wave signal, which is nothing more than a sequence of logic zeros and ones. Frequency of the square signal determines the pitch of the generated sound. To enable buzzer, place jumper JP at E label mark position and to disable buzzer place jumper JP at D Position.

Schematics to Interface Buzzer with CPLD

Buzzer Placement in CPLD Development Kit

VHDL Code Description:

The following VHDL Code demonstrates the functionality of piezo buzzer. PWM pulse is applied with 2s duty cycle. Buzzer produce beeps sound every 1 sec.

VHDL Code for Buzzer Interface with CPLD Development Kit

library IEEE;
entity buzz is
port ( clock : in std_logic;
       a     : out std_logic
end buzz;

architecture Behavioral of buzz is

variable i : integer := 0;
if clock'event and clock = '1' then
if i <= 50000000 then
i := i + 1;
a <= '1';

elsif i > 50000000 and i < 100000000 then
i := i + 1;
a <= '0';

elsif i = 100000000 then
i := 0;  
end if;
end if;
end process;
end Behavioral; 


NET "clock"  LOC = "p181"  ;
NET "a"  LOC = "p123"  ;

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