This paper presents an adaptive encoding framework for the reduction of transition activity in high-capacitance off-chip data buses, since power dissipation associated with those buses can be significant for high-speed communication. The technique relies on the observation of data characteristics over fixed window sizes and formation of cluster with bit lines having highly correlated switching patterns. The proposed method utilizes redundancy in space and time to prevent loss of information while retrieving data. We present analytical and experimental analyses, which demonstrate the activity reduction of our encoding scheme for various data. The extra power cost due to the encoder and decoder circuitry along with redundancy is offset due to reduced number of off-chip transitions.
A CMOS technology progresses into nanometer and sub-nanometer technology, it poses many challenges to design and test engineers. The scaling of VLSI integrated circuits has increased the sensitivity of CMOS technology to cause large power dissipation, propagation delays and various noise mechanisms such as power supply noise, crosstalk noise, leakage noise. The power consumption and crosstalk has become a major concern because of continuing decrease in the minimum feature size and the corresponding increase in chip density and operating frequencies. Most of the power is being wasted on the data buses and long interconnects as dynamic power dissipation for charging and discharging of internal node capacitances and inter-wire capacitances.
Off Chip Communication/Bus:
- Off-chip data buses can be a major power consumer.
- Bus encoding technique is one among the power reduction technique which reduces the dynamic power by reducing the switching activity in off chip wires
- In majority of applications, it is difficult to know the data characteristics in advance, hence the challenge to encode data bus is much higher as compared with address bus.
- In Non Deep submicron technology the load capacitance or the substrate capacitance (CL) between wires to substrate is dominating factor. The coupling capacitance (CC) is between parallel wires which is negligible compare to the load capacitance. Unfortunately in nanometer and sub nanometer technologies the coupling capacitance dominates the load capacitance and its magnitude is several times larger than load capacitance. The characteristics of data buses and long interconnects such as wire spacing , wire length, wire material, wire width, driver strength, coupling length and signal transition time, etc. influences the coupling effect. This increased coupling effect on on-chip buses and on long interconnects not only increase the power dissipation but also deteriorate the signal integrity due to the coupling capacitance. As a results these busses and interconnects becoming more sensitive and prone to errors caused by crosstalk and delay faults .Reducing the power dissipating transitions can also reduces the crosstalk and delay faults. The coupling capacitance also depends upon the data dependent transitions and the coupling effect will increase or decrease depending upon the relative switching activity between adjacent bus wire
A typical analog design flow is as follows:
In case of analog design, the flow changes somewhat.
- Circuit Design
- SPICE Simulation
- Parametric Extraction / Back Annotation
- Final Design
- Tape Out to foundry.