The PS-TYRO-TMS320C67XX is a Low-power digital signal processor based on C674x DSP core. It consumes significantly lower power than other members of the TMS320C6000™ Platform of DSP’s. The C6745/6747 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32KB direct mapped cache and the Level 1 data cache (L1D) is a 32KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 256KB memory space that is shared between program and data space. L2 also has a 1024KB ROM. The evaluation Evolution Board is highly integrated, high-performance solution for demanding control applications and is the first 32-bit 150 MIPS DSP.
Key Features
256K bytes on-chip RAM.
On Board 16M bytes on-chip SDRAM Memory.
Boot ROM (8K x 16) via SCI.
On Board XDS100 Emulator for Execution.
Onboard IEEE 1149.1 JTAG emulation connector.
On Board 25 MHz crystals.
On Board 16K I2C Serial EEPROM.
On Board 512K bytes SPI Flash Memory.
Motor Control Peripherals.
Serial Communications Interfaces (SCIs), UART
On Board 2.7V Dual Channel 12-Bit A/D Converter with SPI Serial Interface.
Up to 109 individually Programmable, Multiplexed General-Purpose Input/output (GPIO) Pins.
12 Digital LED Outputs and 8 Digital Inputs.
Multiple Booting Option DIP Switches.
On Board Reset Switch.
Benefits
300 MHz (6.67-ns Cycle Time).
Fixed/Floating Point Processor.
Advanced Motor control.
Commercial, Industrial or Automotive Temperature.
Signal Processing Applications.
Servo drives and motion control
TEXAS –TMS320C6745
Two Serial Peripheral Interfaces (SPI)
C674x Two Level Cache Memory Architecture
256K-Byte L2 Unified Mapped RAM/Cache.
1024K-Byte L2 ROM.
Kit Includes
Evaluation Board.
5V Power Adaptor.
RS232 Serial Cable,
USB Cable.
CD: Examples, Datasheet, Software ’s, utility.
Download Specification 